This invention relates to a method and apparatus for copying an image stored in one portion of a frame-buffer memory to another portion of the memory in which the first image is self-cleared. In particular, it pertains to a frame-buffer memory apparatus and a method for operating the memory for use with a CRT raster-scanned display when used in a computer graphics system.
The typical display device for a computer system, the CRT, is a raster-scanned device which has no inherent memory. The image that is to appear each time the raster is scanned must be generated by an outside source. Where this image is to be maintained on the screen, such as in a computer graphics system, the information is typically stored in a digital memory. Semiconductor memories are low enough in cost that raster-scanned frame-buffer memories are commonly used. In a frame-buffer memory, each location in the memory corresponds to one picture element on the screen, hereinafter referred to by its common technical term "pixel". This type of memory allows the display hardware to be insensitive to the image content, an arbitrary image can be displayed by properly recording the data at each location in the frame-buffer memory. If it is only necessary to store the presence or absence of illumination of that particular pixel, a two-dimensional memory array is sufficient. If, however, it is desired to control the intensity of the illumination and/or the color of that particular pixel, then a three-dimensional memory is required. In the three-dimensional memory, each location stores a word which is used to store the information to control the intensity and/or color of the pixel. Each time the raster on the CRT is scanned, the video signal to refresh the display is generated from the memory.
Frame-buffer memories were developed as an extension of the memories utilized in general-purpose computers. Accordingly, a typical frame-buffer memory in the prior art was organized into 16 bit words where each bit in the word represents one pixel on the screen. The 16 pixels thus represented by one word of memory were chosen so that they all lie one next to the other along a horizontal scan line of the CRT display. Where a three-dimensional frame-buffer memory is utilized, the memory is typically organized into a series of identical planes. The corresponding location in memory on each plane stores one bit which defines the color and/or the intensity of the illumination of a single pixel. Thus, to obtain the necessary information to illuminate a particular pixel, it is necessary to read the data from the appropriate bit in the word on each of the planes in the three-dimensional memory.
The circuitry which generates the drawing in the frame-buffer memory and thus on the display is generally called a drawing processor. In a lower performance device such as a personal computer, a single microprocessor which is also utilized to run the application program can be utilized to set, clear, AND, OR, and complement bits within the frame-buffer memory to generate the drawing. A higher level approach, such as may be utilized in a computer graphics system, is to utilize a dedicated drawing processor for this task. The drawing processor may be an off-the-shelf part, such as a graphics display controller (GDC) NEC model 7220 manufactured by Nippon Electric Company or it may be built from custom hardware. The highest level approach performs the same job utilizing several drawing processors in parallel to achieve a higher drawing speed.
It should be noted that the development of frame-buffer memories as an extension of the memories utilized in general-purpose computers led in turn to the development of off-the-shelf drawing processor integrated circuits which utilize this memory organization. The great cost saving that such integrated circuit processors provide led to their widespread use. Thus, the operation of frame-buffer memories became tightly linked to the operation of memories for general purpose computers.
As computer graphics became more advanced, there was a need to display symbols or icons on the screen. For example, if the computer graphics system were being utilized to design a digital logic system, the symbols to be displayed would be the logic gates, etc. utilized to construct the logic circuit. It is also common to utilize icons, which are specialized symbols that represent user-selectable functions to be performed by the computer. Thus, it is only necessary to position the cursor on or next to the icon to select the desired function. These symbols and icons may be complex enough and utilized often enough that it is undesirable to have the drawing processor perform the calculations and generate the symbol each time it is to be utilized. Accordingly, a function known as bit block transfer is commonly used. In bit block transfer, the symbol or icon is written into a special portion of the memory which is not utilized to refresh the display. The symbol can be written into a predetermined portion of this "invisible" memory once at the start of the program. Each time the symbol is to be utilized, the symbol is copied from that portion of the memory into the desired portion of the frame-buffer memory and the symbol becomes visible on the display at the desired location. While the symbol may be erased or replaced with another symbol, normally the preselected portion of the "invisible" memory is utilized as a read-only memory to provide the same symbol for use over and over again.
Bit block transfer solves the problem for small, repetitively used symbols. However, it is not generally useful for drawing large, irregularly shaped figures which will not be repetitively used because this would require an "invisible" memory the size of the frame-buffer memory. These figures could be generated, for example, by a program to generate the mask for producing a printed circuit board or a layer of an integrated circuit. These highly complex and generally full-screen figures take a relatively long time to draw when compared to the time required for other computer functions. Thus, the operator is forced to endure the slow on-screen drawing of the figure. In addition to be annoying to the skilled operator, this ties up the operator and the system for the time required to draw the figure.
One known solution to this problem is to utilize one of the planes of a three-dimension frame-buffer memory as a specialized drawing plane. For example, in a frame-buffer memory storing 12 bits to represent each pixel, and therefore having 12 planes, one plane would be utilized as the specialized drawing plane and the other 11 planes utilized in a normal manner to refresh the image on the display. Thus, the complex figure can be drawn in a mode which is "transparent" to the operator; that is, without the operator being aware of this operation. When the drawing processor has completed the complex figure, the figure can be copied to other memory planes in order to provide the color and/or shading that is desired. This feature is sometimes called "bit expansion". This "bit expansion" feature is incorporated in an integrated circuit graphics processing unit, Model 32207, manufactured by AT & T.
The development of frame-buffer memories as an extension of the memories utilized in general-purpose computers was discussed above. In general-purpose computers, the contents of the memory are normally left unchanged after a read operation. This is because when it is desired to change the data in the computer's memory, the new data is simply written over and replaces the existing data. It is not surprising, therefore, that the above-data. identified integrated circuit graphics processing unit provides only a single mode of operation for all of the planes in the frame-buffer memory. Accordingly, when the figure stored in the draw plane is being written into the other planes of the memory, the frame-buffer memory system is in a SET mode.
Frame-buffer memories have different requirements from the memories for general-purpose computers. A common approach for the operation of the drawing processor is to use Bresenham's algorithm. In this approach, the drawing processor accesses a word from memory which contains the first bit of the line to be drawn, modifies the word and writes it back to memory. The drawing processor then calculates the word containing the next bit on the line and repeats the process until the entire line is drawn. If a multidimensional memory array is utilized to permit shading or coloring of the line, then the word in each plane of the memory which contains a bit of the line to be drawn must be accessed and modified. It is necessary to read the word in memory because that word may contain a bit which is representative of another line of the drawing. If we only SET a bit representative of the new line which we wish to draw, then when we write this bit into the memory, the other bits in the word would be cleared to 0 which would result in a portion of the other line of the drawing being removed.
The impact of this requirement is that before a new figure can be drawn, the old figure must be cleared so that no remnants of that figure will appear in the new figure to be drawn. In frame-buffers built with the known memory controllers, this requires a separate erase cycle in which each word in the frame-buffer memory is accessed and cleared to zero.